The skew between any two output channels (commonly referred to as parameter TSKEW) generally refers to the delay between the rising edge of an output clock signal on a first channel and the rising edge of an output clock signal on a second channel. Ideally, this delay should be zero when the phase-locked loop (PLL) or delay-locked loop (DLL) is in a locked operational state. However in reality, due for example to circuit non-idealities, the delay (e.g., parameter TSKEW) will typically never be zero.
A major contributor to the delay (e.g., phase error or skew) is often the mismatch (e.g., device mismatches, wiring mismatches, and/or lithography mismatches) between delays in the individual channels. It is generally preferred to reduce the delay to a minimal amount, but conventional approaches have various drawbacks. For example, one approach attempts to carefully match the different circuit paths and circuit elements across channels to reduce skew, but a significant amount of delay or skew typically remains between channels. As another example, trim circuits may be included to remove additional skew mismatch (e.g., adding or removing capacitance from nodes to increase or decrease delays), but this approach generally does not adequately track process, voltage, and temperature (PVT) conditions.
As a result, there is a need for improved techniques directed to channel-to-channel deskew.